1. Field of the Invention
The invention relates generally to digital systems using a bus master architecture for data exchange. The invention relates more specifically to a method and apparatus for coupling plural communication channels such as Ethernet and SCSI to a local bus such as a PCI local bus.
2a. Limited Waiver of Copyright
This application includes a listing of an HDL (Hardware Descriptor Language) source code for use with a computer program that compiles the source code into an implementation description of corresponding hardware.
In so far as the HDL source code constitutes a copyrightable computer program, the assignee of the present application claims such copyrights in said HDL source code listing. The assignee has no objection, however, to the reproduction by others of this listing if such reproduction is for the sole purpose of studying it to understand the invention. The assignee reserves all other available copyrights in the listing including the right to reproduce the listing as part of a computer program that is in machine-executable form.
2b. Cross Reference to Related Other Publications
The following publication(s) is/are believed to be related to the present application and is/are cited here for purposes of reference:
(a) PCI Local Bus Specification, Revision 2.0, Apr. 30, 1993; available from PCI Special Interest Group, 5200 N. E. Elam Young Parkway, Hillsboro, Oreg. (USA) 97124; and PA1 (b) Verilog-XL.TM. Reference Manual, Version 1.6, March 1991, available from Cadence Design Systems Inc.
2c. Trademark Acknowledgements
VerilogHDL is a trademark of Cadence Software of San Jose, Calif.
Ethernet is a trademark of the Xerox Corporation.
MicroChannel is a trademark of International Business Machines (IBM), Armonk, N.Y.
TRISTATE is a trademark of National Semiconductor, of Sunnyvale, Calif.
Use of these or other trademarks herein does not constitute a claim by the assignee of this application to such marks.
3. Description of the Related Art
Bus master architectures are becoming increasingly popular as a means for the rapid exchange of digital data between data processing and/or transceiving units.
The Small Computer Standard Interface (SCSI) is an example of an industry-standard data exchange architecture in which a form of bus mastering takes place. As many as eight devices can be simultaneously connected to a SCSI bus. One of the eight devices (the bus master) takes control of the shared bus and dictates the direction and routing of a data exchange between itself and another device (target device) on the bus.
Although they are highly popular, the SCSI-1 and SCSI-2 data exchange protocols suffer the problem of not having sufficient bandwidth for voluminous, high-speed data exchanges. The data throughput rate of a SCSI communication channel is constrained by the relatively large, maximum length (approximately 10 meters) that is allowed for SCSI-compliant buses and by the relatively slow pulse rise time (approximately 35 nanoseconds) dictated by line termination specifications.
There is a growing demand in the industry for a data exchange standard that supports a substantially wider communications bandwidth. Part of the demand is owed to an increasing popularity of multimedia applications wherein animated video and sound signals are transmitted and processed together in real-time. Another part of the demand comes from increased reliance on multi-processor systems in which plural data processors are tied together by a high-speed local area network (LAN) such as Ethernet. Yet a further aspect of the growing demand for greater bandwidth arises from continued improvements in the resolution of graphics display systems.
A recently introduced, "PCI local bus" standard promises to expand the data throughput rate of so-called personal computers by a substantial amount. Adoption of the PCI local bus standard is expected to enable high-speed multimedia activities and other operations requiring wide bandwidth. (PCI stands for Peripheral Component Interconnect and the standard is specified by the PCI Special Interest Group of Hillsboro, Oreg. (USA).)
The PCI local bus features a 32-bit wide, multiplexed address-data (AD) bus portion capable of operating at up to 132 megabytes per second (132 MB/s peak). An already-defined, performance upgrade path allows for expansion to a 64-bit wide AD bus portion capable of operating at up to 264 MB/s peak.
PCI bus access is based on arbitration between contending agents. Each device (agent) that wants to be a bus-master issues a bus-master request (REQ#) to a central arbiter. The central bus arbiter returns an active bus-grant (GNT#) signal to the winner. The arbitration scheme can be based on a rotating priority or on another fair scheme.
A large number of devices (agents) may be found simultaneously contending for access to a PCI local bus in a high performance computer system. Examples of such potential contenders include, but are not limited to, a SCSI adaptor module, an Ethernet interface module, a CPU-to-memory bridge unit, a motion video processing unit, a sound processing unit, and an expansion bus interface unit (e.g., an EISA-to-PCI interface).
A problem develops when designers want to couple more than a few devices (e.g., more than 10 "loads") to a PCI local bus. The high data throughput rate of the PCI local bus is due in part to a fixed limitation that is placed on the number of electrical AC and DC "loads" that can be attached to the bus while still maintaining peak performance (e.g., a 33 MHz clock rate). The speed of the PCI local bus is owed in further part to another limitation that is placed on the physical length and on the capacitance of the conductor traces and connection pins that define the bus. Each PCI "load" typically has a capacitance of between 15 to 25 picofarads (15-25 pF) per pin. The electrical-load, capacitance, and physical-size parameters of a PCI-compliant bus have to be jointly configured in order to assure a clock skew of less than a prespecified first amount (2 nS) for synchronous operations between any two bus devices and a data signal propagation time of less than a second prespecified amount (10 nS). Thus there are physical and electrical constraints which limit the number of attachment slots and input/output buffers that may be provided along a PCI local bus.
Current technology appears to allow for no more than four expansion slots on any one PCI local bus. Each combination of a conventional expansion connector plus a conventional expansion board consumes two "loads". Each IC chip that connects directly to the PCI local bus consumes one "load". The PCI local bus is allowed no more than 10 loads under current specifications. Thus, four expansion slots and one direct-connect IC consume 9 of the 10 allowed loads. It appears that the number devices that designers may soon wish to attach to the PCI bus will quickly exceed the 10 load maximum. A need is developing within the industry for being able to couple many different device drivers such as SCSI, Ethernet, real-time audio/video, cache memory, expansion buses such as EISA, VESA or MicroChannel, and so forth onto the PCI local bus or onto a like, load-and-size constrained local bus, while giving each attached device an appropriate opportunity to act as a bus-master.